3D Interconnect Architectures for Heterogeneous Technologies

Part I Introduction.- 1 Introduction to 3D Technologies.- 1.1 Motivation for Heterogenous 3D ICs.- 1.2 3D Technologies.- 1.3 TSV Capacitances-A Problem Resistant to Scaling.- 1.4 Conclusion.- 2 Interconnect Architectures for 3D Technologies.- 2.1 Interconnect Architectures.- 2.2 Overview of Interconnect Architectures for 3D ICs.- 2.3 Three-dimensional Networks on chips.- 2.4 Conclusion.- Part II 3D Technology Modeling.- 3 Power and Performance Formulas.- 3.1 High-Level Formula for the Power Consumption.- 3.2 High-Level Formula for the Propagation Delay.- 3.3 Matrix Formulations.- 3.4 Evaluation.- 3.5 Conclusion.- 4 Capacitance Estimation.- 4.1 Existing Capacitance Models.- 4.2 Edge and MOS Effects on the TSV Capacitances.- 4.3 TSV Capacitance Model.- 4.4 Evaluation.- 4.5 Conclusion.- Part III System Modeling.- xiii.- xiv Contents.- 5 Application and Simulation Models.- 5.1 Overview of the Modeling Approach.- 5.2 Application Traffic Model.- 5.3 Simulation Model of 3D NoCs.- 5.4 Simulator Interfaces.- 5.5 Conclusion.- 6 Bit-level Statistics.- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for.- Single Data Streams.- 6.2 Data-Stream Multiplexing.- 6.3 Bit-Level Statistics with Data-Stream Multiplexing.- 6.4 Evaluation.- 6.5 Conclusion.- 7 Ratatoskr Framework.- 7.1 Ratatoskr for Practitioners.- 7.2 Implementation.- 7.3 Evaluation.- 7.4 Case Study: Link Power Estimation and Optimization.- 7.5 Conclusion.- Part IV 3D-Interconnect Optimization.- 8 Low-Power Technique for 3D Interconnects.- 8.1 Fundamental Idea.- 8.2 Power-Optimal TSV assignment.- 8.3 Systematic Net-to-TSV Assignments.- 8.4 Combination with Traditional Low-Power Codes.- 8.5 Evaluation.- 8.6 Conclusion.- 9 Low-Power Technique for High-Performance 3D.- Interconnects..- 9.1 Edge-Effect-Aware Crosstalk Classification.- 9.2 Existing Approaches and Their Limitations.- 9.3 Proposed Technique.- 9.4 Extension to a Low-Power3D CAC.-

Lennart Bamberg received the B.Sc., M.Sc., and Ph.D. (Dr.-Ing. ) degree with highest honours ("summa cum laude") in electrical and computer engineering from the University of Bremen, Germany, in 2014, 2016, and 2020, respectively. In 2019, he was a Visiting Research Scholar at the Georgia Institute of Technology, Atlanta (USA). This stay was funded by a scholarship of the German Academic Exchange Service, DAAD, and the German Federal Ministry of Education and Research, BMBF. Afterwards, he was a Technical director at GrAI Matter Labs, where he was in charge of the processor architecture for edge AI. Since 2022, he is System Architect at NXP Semiconductors working on secure-element SoCs for mobile phones and wearables. In parallel, he serves as a guest lecturer at the University of Bremen in electrical engineering since 2020. Lennart Bamberg's research interests include low-power and domain-specific computer architectures for embedded systems. He received best-paper awards atinternational conferences and serves as a reviewer and program-committee member for several international conferences and journals.

Jan Moritz Joseph got his B.Sc. in medical engineering in 2011 and his M.Sc. in computer science in 2014 from the Universität zu Lübeck, Germany.  From 2008 to 2014 he was a scholarship holder of the German Merit Foundation (Deutsche Studienstiftung e.V.). Dr. Joseph received his Ph.D. from Otto-von-Guericke Universität Magdeburg, Germany, in 2019. The title of his thesis was "Networks-on-Chip for heterogeneous 3D Systems-on-Chip". His Ph.D. was awarded the highest honours "summa cum laude". In 2020, he received the award for the best PhD thesis from the Faculty of Electrical Engineering and Information Technology at Otto-von-Guericke Universität Magdeburg, Germany. From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna's Synergy Lab at Georgia Institute of Technology, Atlanta, GA. His stay was partially funded by a