A High Performance Low Power Universal Gate Implementation
in sub threshold region
(Sprache: Englisch)
a new power reduction technique called Voltage Scaling Stacked Transistor (VS-STACK) has been presented. The proposed technique has been compared with some of the existing power reduction techniques. The result shows a colossal amount of reduction in power...
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a new power reduction technique called Voltage Scaling Stacked Transistor (VS-STACK) has been presented. The proposed technique has been compared with some of the existing power reduction techniques. The result shows a colossal amount of reduction in power consumption for the 2input NOR gate. The power consumption is curtailed by 20% to 90%. Furthermore there is a tremendous improvement in the power delay product. Hence this technique can be used for high speed circuits. The circuit operates in subthreshold region which is suitable for applications that require extremely low power consumption
Autoren-Porträt von Geetanjali Sharma
Sharma, GeetanjaliGeetanjali Sharma has 12 years of teaching and research experience in the field of Electronics & Communication and VLSI Design. She has several publications in international journals and conferences in VLSI Design field.
Bibliographische Angaben
- Autor: Geetanjali Sharma
- 2019, 60 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 620028170X
- ISBN-13: 9786200281708
Sprache:
Englisch
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