CONPAR '90, VAPP IV
Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, September 10-13, 1990. Proceedings
(Sprache: Englisch)
Parallel architectures are no longer pure research vehicles, as they were some years ago. There are now many commercial systems competing for market segments in scientific computing. The 1990s are likely to become the decade of parallel processing. CONPAR...
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Klappentext zu „CONPAR '90, VAPP IV “
Parallel architectures are no longer pure research vehicles, as they were some years ago. There are now many commercial systems competing for market segments in scientific computing. The 1990s are likely to become the decade of parallel processing. CONPAR 90 - VAPP IV is the joint successor meeting of two highly successful international conference series in the field of vector and parallel processing. This volume contains the 79 papers presented at the conference. The various topics of the papers include hardware, software and application issues. Some of the session titles best reflect the contents: new models of computation, logic programming, large-grain data flow, interconnection networks, communication issues, reconfigurable and scalable systems, novel architectures and languages, high performance systems and accelerators, performance prediction / analysis / measurement, performance monitoring and debugging, compile-time analysis and restructurers, load balancing, process partitioning and concurrency control, visualization and runtime analysis, parallel linear algebra, architectures for image processing, efficient use of vector computers, transputer tools and applications, array processors, algorithmic studies for hypercube-type systems, systolic arrays and algorithms. The volume gives a comprehensive view of the state of the art in a field of current interest.
Inhaltsverzeichnis zu „CONPAR '90, VAPP IV “
- Digital electronics for 50 years: No limits to growth?- Parallel computing : An Indian perspective
- POOMA, POOL and parallel symbolic computing: An assessment
- A decoupled data-driven architecture with vectors and macro actors
- A novel paradigm of parallel computation and its use to implement simple high performance hardware
- Presto: A bus-connected multiprocessor for a rete-based production system
- A model for performance prediction of message passing multiprocessors achieving concurrency by domain decomposition
- Workloads, observables, benchmarks and instrumentation
- A method for performance prediction of parallel programs
- Divide and conquer: A new parallel algorithm for the solution of a tridiagonal linear system of equations
- Sparse matrix algorithms for SUPRENUM
- Parallel givens factorization on a shared memory multiprocessor
- Study of a parallel inference machine for parallel execution of logic programs
- Parallel implementation of logic languages
- Prolog implementations on parallel computers
- Performance evaluation of parallel programs in parallel and distributed systems
- The ELAN performance analysis environment
- Monitoring and debugging Transputer-networks with NETMON-II
- An adaptive blocking strategy for matrix factorizations
- Factorizations of band matrices using level 3 BLAS
- On the computation of breeding values
- Code parallelization for the LGDG large-grain dataflow computation
- Development of portable parallel programs with large-grain data flow 2
- ADAM: a coarse-grain dataflow architecture that addresses the load balancing and throttling problems
- A latency tolerant code generation algorithm for a coarse grain dataflow machine
- Cedar Fortrand its compiler
- Optimizing communication in SUPERB
- A design of performance-optimized control-based synchronization
- Interprocess analysis and optimization in the equational language compiler
- Transputer based distributed cartographic image processing
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... mehr
MPS-an experimental multi-microprocessor based parallel system
- Parallel implementation of the convolution method in image reconstruction
- SYDAMA II: A heterogeneous multiprocessor system for real time image processing
- Analysis and design of circuit switching interconnection networks using 4×4 nodes
- Design and simulation of a multistage interconnection network
- A reconfigurable interconnection network for flexible pipelining
- A fast distributed mapping algorithm
- A note on the load balancing problem for coarse grained hypercube dictionary machines
- Hierarchical wiring in multigrids
- Optimal data structures for an efficient vectorized finite element code
- FFTVPLIB, a collection of Fast Fourier transforms for vectorprocessors
- Improving the vector performance via algorithmic domain decomposition
- Implementation of parallel numerical routines using broadcast communication schemes
- A process and memory model for a parallel distributed-memory machine
- A deadlock free routing algorithm with network size independent buffering space
- From object-oriented programming to automatic load distribution
- Partitioning programs into processes
- An MIMD execution environment with a fixed number of processes
- Sorting large data files on POOMA
- Parallelizing divide-and-conquer algorithms - Microtasking versus autotasking
- The performance of linear algebra subprograms on the siemens S series
- A family of highly parallel computers
- A distributed shared memory multiprocessor kit with scalable local complexity
- Scalable cache coherence for large shared memory multiprocessors
- Design and implementation of an exception handling mechanism for communicating sequential processes
- Creating and controlling concurrency in object oriented systems - A case study -
- A distributed algorithm for dynamic task scheduling
- TéNOR++: A dynamic configurer for SuperNode machines
- Parallel modelling of electromagnetic field scattering: A new approach using the Edinburgh concurrent supercomputer facility
- 3D multigrid correction methods for Transputer networks
- A comparative study of two wavefront implementations of a LU solver algorithm
- Systolic array architecture for two-dimensional discrete Fourier transform
- Design and implementation of M1 Cellprocessor
- A comparison of microtasking implementations of the applicative language SISAL
- An efficient scheme for fine-grain software pipelining
- Sisal on a message passing architecture
- The TOPSYS architecture
- MMK - A distributed operating system kernel with integrated dynamic loadbalancing
- The distributed monitor system of TOPSYS
- Hybrid algorithms for the elgensolution of large sparse symmetric matrices on the AMT DAP 510
- Virtual systems architecture on the AMT DAP
- Numerical simulation of thermal convection on SIMD computers
- Massively parallel realization of logical operations in distributed parallel systems
- High-performance computer system "Siberia"
- EDS hardware architecture
- Visualizing and analysing the runtime behavior of parallel programs
- PATOP for performance tuning of parallel programs
- Real-time visualization of concurrent processes
- Achieving superlinear speedups for the multiple polynomial quadratic sieve factoring algorithm on a distributed memory multiprocessor
- A performance analysis of network topologies in finding the roots of a polynomial
- Parallel multigrid algorithms for some specialized computer systems
- Computation race at CONPAR 90, VAPP IV ETH Zurich, Sep 10-13, 1990
- Parallel implementation of the convolution method in image reconstruction
- SYDAMA II: A heterogeneous multiprocessor system for real time image processing
- Analysis and design of circuit switching interconnection networks using 4×4 nodes
- Design and simulation of a multistage interconnection network
- A reconfigurable interconnection network for flexible pipelining
- A fast distributed mapping algorithm
- A note on the load balancing problem for coarse grained hypercube dictionary machines
- Hierarchical wiring in multigrids
- Optimal data structures for an efficient vectorized finite element code
- FFTVPLIB, a collection of Fast Fourier transforms for vectorprocessors
- Improving the vector performance via algorithmic domain decomposition
- Implementation of parallel numerical routines using broadcast communication schemes
- A process and memory model for a parallel distributed-memory machine
- A deadlock free routing algorithm with network size independent buffering space
- From object-oriented programming to automatic load distribution
- Partitioning programs into processes
- An MIMD execution environment with a fixed number of processes
- Sorting large data files on POOMA
- Parallelizing divide-and-conquer algorithms - Microtasking versus autotasking
- The performance of linear algebra subprograms on the siemens S series
- A family of highly parallel computers
- A distributed shared memory multiprocessor kit with scalable local complexity
- Scalable cache coherence for large shared memory multiprocessors
- Design and implementation of an exception handling mechanism for communicating sequential processes
- Creating and controlling concurrency in object oriented systems - A case study -
- A distributed algorithm for dynamic task scheduling
- TéNOR++: A dynamic configurer for SuperNode machines
- Parallel modelling of electromagnetic field scattering: A new approach using the Edinburgh concurrent supercomputer facility
- 3D multigrid correction methods for Transputer networks
- A comparative study of two wavefront implementations of a LU solver algorithm
- Systolic array architecture for two-dimensional discrete Fourier transform
- Design and implementation of M1 Cellprocessor
- A comparison of microtasking implementations of the applicative language SISAL
- An efficient scheme for fine-grain software pipelining
- Sisal on a message passing architecture
- The TOPSYS architecture
- MMK - A distributed operating system kernel with integrated dynamic loadbalancing
- The distributed monitor system of TOPSYS
- Hybrid algorithms for the elgensolution of large sparse symmetric matrices on the AMT DAP 510
- Virtual systems architecture on the AMT DAP
- Numerical simulation of thermal convection on SIMD computers
- Massively parallel realization of logical operations in distributed parallel systems
- High-performance computer system "Siberia"
- EDS hardware architecture
- Visualizing and analysing the runtime behavior of parallel programs
- PATOP for performance tuning of parallel programs
- Real-time visualization of concurrent processes
- Achieving superlinear speedups for the multiple polynomial quadratic sieve factoring algorithm on a distributed memory multiprocessor
- A performance analysis of network topologies in finding the roots of a polynomial
- Parallel multigrid algorithms for some specialized computer systems
- Computation race at CONPAR 90, VAPP IV ETH Zurich, Sep 10-13, 1990
... weniger
Bibliographische Angaben
- 1990, XIV, 900 Seiten, Maße: 17,2 x 24,4 cm, Kartoniert (TB), Englisch
- Herausgegeben: Helmar Burkhart
- Verlag: Springer Berlin
- ISBN-10: 3540530657
- ISBN-13: 9783540530657
- Erscheinungsdatum: 30.08.1990
Sprache:
Englisch
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