Design for AT-Speed Test, Diagnosis and Measurement
(Sprache: Englisch)
Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board...
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Klappentext zu „Design for AT-Speed Test, Diagnosis and Measurement “
Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a `must read' before any DFT is attempted.
Inhaltsverzeichnis zu „Design for AT-Speed Test, Diagnosis and Measurement “
Technology Overview.- Memory Test and Diagnosis.- Logic Test and Diagnosis.- Embedded Test Design Flow.- Hierarchical Core Test.- Test and Measurement for PLLs and ADCs.- System Test and Diagnosis.- System Reuse of Embedded Test.
Bibliographische Angaben
- 2013, 2000, XVII, 239 Seiten, Maße: 17,8 x 25,4 cm, Kartoniert (TB), Englisch
- Herausgegeben: Benoit Nadeau-Dostie
- Verlag: Springer, Berlin
- ISBN-10: 1475782918
- ISBN-13: 9781475782912
Sprache:
Englisch
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