Designing 2D and 3D Network-on-Chip Architectures
(Sprache: Englisch)
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for...
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Klappentext zu „Designing 2D and 3D Network-on-Chip Architectures “
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
Inhaltsverzeichnis zu „Designing 2D and 3D Network-on-Chip Architectures “
Part I: Network-on-Chip Design Methodology.- Network-on-Chip Technology: A Paradigm Shift.- NoC Modeling and Topology Exploration.- Communication Architecture.- Power and Thermal Effects and Management.- NoC-based System Integration.- NoC Verification and Testing.- The Spidergon STNoC.- Middleware Memory Management in NoC.- On Designing 3-D Platforms.- The SYSMANTIC NoC Design and Prototyping Framework.- Part II: Suggested Projects.- Projects on Network-on Chip.
Bibliographische Angaben
- Autoren: Konstantinos Tatas , Kostas Siozios , Dimitrios Soudris , Axel Jantsch
- 2014, Softcover reprint of the original 1st ed. 2014, 265 Seiten, 79 farbige Abbildungen, Maße: 15,6 x 1,6 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1493945505
- ISBN-13: 9781493945504
Sprache:
Englisch
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