Low-Power Deep Sub-Micron CMOS Logic, w. CD-ROM
Sub-threshold Current Reduction
(Sprache: Englisch)
The strong interaction between the demand for increasing chip functionality and data-processing speeds, and technological trends in the integrated circuit industry, like e.g. shrinking device geometry, growing chip area and increased transistor switching...
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The strong interaction between the demand for increasing chip functionality and data-processing speeds, and technological trends in the integrated circuit industry, like e.g. shrinking device geometry, growing chip area and increased transistor switching speeds, cause a huge increase in power dissipation for deep sub-micron digital CMOS circuits.
Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction classifies all power dissipation sources in digital CMOS circuits and provides for a systematic approach of power reduction techniques. A clear distinction has been made between power dissipated to perform a calculation in a certain time frame, i.e. functional power dissipation, and power dissipated even when a circuit is idle, i.e. parasitical power dissipation. The threshold voltage level forms an important link between the functional and the parasitical power dissipation. Since for high data-processing speeds the threshold voltage needs to be low, whereas for low sub-threshold leakage currents it needs to be high. The latter is extremely important for battery operated circuits in standby modes. Therefore, a separate classification of sub-threshold current reduction techniques is presented showing existing and new circuit topologies.
Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction is a valuable book for researchers, designers as well as students in the field of low-power digital design. Power dissipation is discussed from a fundamental, quantum mechanical and a practical point of view. Theory is accompanied with practical circuit implementations and measurement results.
Klappentext zu „Low-Power Deep Sub-Micron CMOS Logic, w. CD-ROM “
1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.
Inhaltsverzeichnis zu „Low-Power Deep Sub-Micron CMOS Logic, w. CD-ROM “
- Index of Symbols1. Introduction
2. Power Versus Energy
3. Power Dissipation in Digital CMOS Circuits
4. Reduction of Functional Power Dissipation
5. Reduction of Parasitical Power Dissipation
6. Weak-inversion Current Reduction
7. Effectiveness of Weak-inversion Current Reductions
8. Triple-S Circuit Designs
9. Conclusions
10. Summary
- References
- Index
Bibliographische Angaben
- Autoren: P. van der Meer , A. van Staveren , Arthur H.M. van Roermund
- 2005, XIV, 154 Seiten, Maße: 16 x 24,6 cm, Gebunden, Englisch
- Verlag: Springer Netherlands
- ISBN-10: 1402028482
- ISBN-13: 9781402028489
Sprache:
Englisch
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