Low-Power High-Speed Adcs for Nanometer CMOS Integration
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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.
- Autoren: Zhiheng Cao , Shouli Yan
- 2008, 95 Seiten, Maße: 16,7 x 24,4 cm, Gebunden, Englisch
- Verlag: Springer Netherland
- ISBN-10: 1402084498
- ISBN-13: 9781402084492
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