Source-Synchronous Networks-On-Chip
Circuit and Architectural Interconnect Modeling
(Sprache: Englisch)
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. It provides circuit-level details of the NoC and includes architectural simulations of the NoC.
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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. It provides circuit-level details of the NoC and includes architectural simulations of the NoC.
Klappentext zu „Source-Synchronous Networks-On-Chip “
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
Inhaltsverzeichnis zu „Source-Synchronous Networks-On-Chip “
Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.
Bibliographische Angaben
- Autoren: Ayan Mandal , Sunil P Khatri , Rabi Mahapatra
- 2014, Softcover reprint of the original 1st ed. 2014, XIII, 143 Seiten, 10 farbige Abbildungen, Maße: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1493948172
- ISBN-13: 9781493948178
Sprache:
Englisch
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