The Simple Art of SoC Design
Closing the Gap between RTL and ESL
(Sprache: Englisch)
This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques...
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This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow's SoC designs.
Klappentext zu „The Simple Art of SoC Design “
This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow's SoC designs.
Inhaltsverzeichnis zu „The Simple Art of SoC Design “
The Challenges of Complex Design; Simplifying RTL Design; Reducing Complexity in Control-Dominated Designs; Hierarchical State Machines; More on State Space; Verification; Reducing Complexity in Data Path Dominated Designs; Simplifying Interfaces; Complexity at the Chip Level; Raising Abstraction Above RTL; SystemVerilog Extensions; The Future of Design.
Autoren-Porträt von Synopsys Fellow, Michael Keating
Mike Keating is a Synopsys Fellow. Over the last 12 years, he has been with Synopsys focusing on IP development methodology, hardware and software design quality and low power design. His current research focuses on high level design and the challenges of designing extremely complex systems. Mike received his BSEE and MSEE from Stanford University, and has over 25 years experience in ASIC and system design. He is co-author of the Reuse Methodology Manual and the Low Power Methodology Manual. In 2007, ISQED gave Mike the Quality Award for contributions to quality in electronic design.
Bibliographische Angaben
- Autor: Synopsys Fellow, Michael Keating
- 2011, XVII, 234 Seiten, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1441985859
- ISBN-13: 9781441985859
- Erscheinungsdatum: 19.05.2011
Sprache:
Englisch
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