The Verilog® Hardware Description Language
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(Sprache: Englisch)
xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral...
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Klappentext zu „The Verilog® Hardware Description Language “
xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
Inhaltsverzeichnis zu „The Verilog® Hardware Description Language “
Verilog - A Tutorial Introduction.- Logic Synthesis.- Behavioral Modeling.- Concurrent Processes.- Module Hierarchy.- Logic Level Modeling.- Cycle-Accurate Specification.- Advanced Timing.- User-Defined Primitives.- Switch Level Modeling.- Projects.
Bibliographische Angaben
- Autoren: Donald E. Thomas , Philip R. Moorby
- 2014, 5. Aufl., XXII, 382 Seiten, Maße: 15,5 x 23,4 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 147577589X
- ISBN-13: 9781475775891
Sprache:
Englisch
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