Transactions on High-Performance Embedded Architectures and Compilers V
(Sprache: Englisch)
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose...
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Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.This 5th issue contains extended versions of papers by the best paper award candidates of IC-SAMOS 2009 and the SAMOS 2009 Workshop, colocated events of the 9th International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2009, held in Samos, Greece, in 2009. The 7 papers included in this volume were carefully reviewed and selected. The papers cover research on embedded processor hardware/software design and integration and present challenging research trends.
Inhaltsverzeichnis zu „Transactions on High-Performance Embedded Architectures and Compilers V “
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.-Programmable and Scalable Architecture for Graphics Processing Units.- Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs.- A Hardware-Accelerated Estimation-Based Power Profiling Unit. - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management.- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.- Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability.- A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.
Bibliographische Angaben
- 2019, 1st ed. 2019, IX, 141 Seiten, 36 farbige Abbildungen, Maße: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Herausgegeben: Per Stenström, Cristina Silvano, Koen Bertels, Michael Schulte
- Verlag: Springer, Berlin
- ISBN-10: 3662588331
- ISBN-13: 9783662588338
- Erscheinungsdatum: 29.03.2019
Sprache:
Englisch
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