A Pipelined Multi-Core Machine with Operating System Support / Lecture Notes in Computer Science Bd.9999 (PDF)
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate...
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This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
. MIPS instruction set architecture (ISA) for application and for system programming
. cache coherent memory system
. store buffers in front of the data caches
. interrupts and exceptions
. memory management units (MMUs)
. pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
. local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
. I/O-interrupt controller and a disk
- Autoren: Petro Lutsyk , Jonas Oberhauser , Wolfgang J. Paul
- 2020, 1st ed. 2020, 628 Seiten, Englisch
- Verlag: Springer-Verlag GmbH
- ISBN-10: 3030432432
- ISBN-13: 9783030432430
- Erscheinungsdatum: 09.05.2020
Abhängig von Bildschirmgröße und eingestellter Schriftgröße kann die Seitenzahl auf Ihrem Lesegerät variieren.
- Dateiformat: PDF
- Größe: 13 MB
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