Energy Efficient and Reliable Embedded Nanoscale SRAM Design (PDF)

associated with the Department Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta USA for a period of one year. Prior to joining MU, he was an Analog Design Engineer (SRAM Design) at Intel Microelectronics, Penang, Malaysia. Over there his his primary work included designing SRAM circuits, Pre-layout SRAM design and analysis of its various design parameters i.e. read margin/write margin, critical path, read/write performance, dynamic and leakage power at different PVT values for Intel's 7nm and 10nm FPGAs. His primary research work includes designing low power and robust SRAM for space applications, In-Memory compute and for IoT devices.

Dr. Ambika Prasad Shah is currently working as an Assistant Professor, Electrical Engineering Department, and Associate Dean Corporate Relations at Indian Institute of Technology Jammu, India. He received Ph.D. degree from the Electrical Engineering Department, Indian Institute of Technology Indore, India. Before joining IIT Jammu, Dr. Shah worked as a Postdoctoral Fellow at the Institute for Microelectronics, TU Vienna, Austria. He is the recipient of the Young Scientist Award from the M.P. Council of Science and Technology Bhopal, M.P. India. He has authored/co-authored more than 70 research papers in peer-reviewed international journals and conferences. He was the Conference Organizing Chair for VDAT-2022 and Fellowship Chair for VLSID-2022. He is a fellow of IETE, senior member of IEEE, and member of ACM, ISTE, ISCA, IEI, and IAENG.

His current research interest includes reliability analysis of digital circuits, Design for reliability, fault-tolerant circuits, reliability modeling, low power high-performance circuit designs, and Hardware Security circuits.

Prof. Santosh Kumar Vishvakarma is with the Department of Electrical Engineering, Indian Institute of Technology Indore, MP, India as Professor. He is engaged with teaching and research in the area of Energy-Efficient and Reliable SRAM Memory Design, Enhancing Performance and Configurable Architecture for DNN Accelerators, SRAM based In-Memory Computing Architecture for Edge AI, Reliable, Secure Design for IoT Application, Design for Reliability. Prof. Vishvakarma is the reviewer of various Journals like IEEE Transaction on Electron Devices, IEEE Transaction on Nanotechnology, IEEE Transaction on VLSI Integration System, Elsevier Microelectronics Journal, Elsevier Integration the VLSI Journal, IEEE Transaction on VLSI Integration System, Analog Integrated Circuits and Signal Processing Springer, Circuits, Systems & Signal Processing (CSSP), Solid State Electronics etc. He is a Member of IEEE, Professional Member of VLSI Society of India, Associate Member of Institute of Nanotechnology, Life member of Indian Microelectronics Society (IMS), India.

He is the General Chair of 23rd International Symposium on VLSI Design and Test (VDAT-2019) On July 4-6, 2019, IIT Indore, India.

Prof. Vishvakarma did schooling from Gorakhpur itself and then Bachelor of Science (B.Sc.) in Electronics, Master of Science (M.Sc.) in Electronics and Master of Technology (M.Tech.) in Microelectronics from University of Gorakhpur, Devi Ahilya Vishvidayalaya Indore and Panjab University Chandigarh in 1999, 2001 and 2003 respectively. Dr. Vishvakarma obtained Ph.D. degree on the topic "Analytical Modeling of Low Leakage MGDG MOSFET and its Application to SRAM" from Microelectronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee (IITR) in 2010 and worked under the supervision of Prof. S. Dasgupta, & Prof. A. K. Saxena in the area of MOS device modeling and SRAM circuit design.