SVA: The Power of Assertions in SystemVerilog (PDF)
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This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012
SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.
· Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA);
· Includes step-by-step examples of how SVA can be used to construct powerful and reusable sets of properties;
· Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard.
Surrendra Dudani received M.S. and Ph.D. degrees in electrical & computer engineering from Syracuse University, NY, in 1976 and 1980, respectively. From 1980 until 1989, he worked at Honeywell, Prime Computers and Stardent Computers as a Principal Engineer. He developed various design verification languages, CAD tools and methodologies. In 1990, he founded Pragmatics Computing to provide consulting services to hardware and software companies. He pioneered code coverage technology for design verification and introduced one of the first products in the market. He joined Synopsys, Inc., in 1999. Currently he is a Scientist in the Marlborough, MA, office as member of the Synopsys Verification Group. His current responsibilities include developing and managing assertions technology and other techniques for design verification. He holds three patents and has published many papers at conferences. He was a member of the IEEE P1800 System Verilog Assertions committee and a co-author of The Power of System Verilog Assertions
John Havlicek earned a B.S. in Mathematics from Ohio State (1987) and a Ph.D. in Mathematics from Stanford (1992). From 1996 to 2000, he pursued doctoral studies in Computer Sciences at the University of Texas, working on formal methods with E. Allen Emerson. He then joined Motorola Semiconductor and began work on tools and methodologies for semiconductor design verification. He has worked to expand the deployment of assertions both in simulation and formal verification and has been active in the creation and standardization of industrial assertion languages, notably IEEE 1850 PSL and IEEE 1800 System Verilog Assertions. He served as chair of the System Verilog Assertions Committee, served on the System Verilog Champions Committee and helped to found the System Verilog Discrete Committee. He was a primary author of enhancements to coverage modeling capabilities in the 2012 System Verilog standard. He also worked in a subgroup of the Verilog-AMS Committee to study assertion constructs for analog and mixed-signal verification. Currently, he works for Cadence Design Systems in the Design IP Team for DDR Memory Controller and PHY. As diversions, John enjoys early music, backpacking and amateur astronomy.
Dmitry Korchemny earned an MSc. in electrical engineering and computer science from Moscow Institute of Radio-engineering, Electronics and Automation in 1984. He joined Intel in 1993. Currently he is a senior CAD technical staff engineer at Intel. His interests include pre- and post-Si verification, debug and test generation. He is actively involved into System Verilog Assertion standardization and he is a chair of Assertion Committee of IEEE P1800 Working Group.
- Autoren: Eduard Cerny , Surrendra Dudani , John Havlicek , Dmitry Korchemny
- 2014, 2nd ed. 2015, 590 Seiten, Englisch
- Verlag: Springer-Verlag GmbH
- ISBN-10: 3319071394
- ISBN-13: 9783319071398
- Erscheinungsdatum: 23.08.2014
Abhängig von Bildschirmgröße und eingestellter Schriftgröße kann die Seitenzahl auf Ihrem Lesegerät variieren.
- Dateiformat: PDF
- Größe: 5.88 MB
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