Advances in Computer Systems Architecture

Flexible Architecture for Color Image Enhancement.- Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three.- PMPS(3): A Performance Model of Parallel Systems.- Issues and Support for Dynamic Register Allocation.- A Heterogeneous Multi-core Processor Architecture for High Performance Computing.- Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation.- Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes.- Constructing Node-Disjoint Paths in Enhanced Pyramid Networks.- Striping Cache: A Global Cache for Striped Network File System.- DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing.- The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier.- Live Range Aware Cache Architecture.- The Challenges of Efficient Code-Generation for Massively Parallel Architectures.- Reliable Systolic Computing Through Redundancy.- A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks.- A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling.- On the Reliability of Drowsy Instruction Caches.- Design of a Reconfigurable Cryptographic Engine.- Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors.- The New BCD Subtractor and Its Reversible Logic Implementation.- Power-Efficient Microkernel of Embedded Operating System on Chip.- Understanding Prediction Limits Through Unbiased Branches.- Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP.- Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks.- Cycle Period Analysis and Optimization of Timed Circuits.- Acceleration Techniques for Chip-Multiprocessor Simulator Debug.- A DDL-Based Software Architecture Model.- Branch Behavior Characterization for Multimedia Applications.- Optimization and Evaluating of StreamYGX2 on MASA Stream Processor.- SecureTorrent: A Security Framework for File Swarming.- Register Allocation on Stream Processor with Local Register File.- A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance.- Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture.- Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.- Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.- Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols.- An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.- An Efficient Approach to Energy Saving in Microcontrollers.