Counterfeit Integrated Circuits

Introduction.- Conterfeit Integrated Circuits.- Counterfeit Defects.- Physical Tests for Counterfeit Detection.- Electrical Tests for Counterfeit Detection.- Counterfeit Test Coverage: An Assessment of Current Counterfeit Detection Methods.- Advanced Detection: Physical Tests.- Advanced Detection: Electrical Tests.- Combating Die and IC Recycling.- Hardware IP Watermarking.- Prevention of Unlicensed and Rejected ICs from Untrusted Foundry and Assembly.- Chip ID.

Mark (Mohammad) Tehranipoor is currently the Charles H. Knapp Associate Professor of Electrical and Computer Engineering Department at the University of Connecticut.

His current research projects include: computer-aided design and test for CMOS VLSI designs, hardware security and trust, counterfeit IC detection and prevention, and reliable systems design at nanoscale. Prof. Tehranipoor has published over 200 journal articles and refereed conference papers and has given more than 125 invited talks and keynote addresses since 2006. In addition, he has published five books and ten book chapters. His projects are sponsored by both the industry (SRC, Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Cisco, Qualcomm, MediaTeck, etc.) and Government (NSF, ARO, MDA, DOD, DOE, etc.).

He is a recipient of several best paper awards, the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2010 IEEE CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2009 NSF CAREER Award, the 2009 UConn ECE Research Excellence Award, and the 2012 UConn SOE Outstanding Faculty Advisor Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, and IEEE Computer Society Computing Now. He served as Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011.

He co-founded a new symposium called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) ()http://www.engr.uconn.edu/HOST/) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair

"In this book, the authors present an overall description of the physical and electrical techniques that are used in the state of the art. Those techniques are proven to be useful in the practical detection and avoidance of counterfeit ICs. ... usable as a handbook for engineers and experts in this field." (Zheng Gong, computing Reviews, August, 2015)