Digital Signal Processing 101

1. Numerical Representation 2. Complex Numbers and Exponentials 3. Sampling, Aliasing and Quantization 4. Frequency Response 5. Finite Impulse Response (FIR) Filters 6. Windowing 7. Decimation and Interpolation 8. Infinite Impulse Response (IIR) Filters 9. Matrix Inversion algorithms (QR and Cholesky Decomposition) 10. Complex Modulation and Demodulation 11. Discrete and Fast Fourier Transforms (DFT, FFT) 12. Discrete Cosine Transform (DCT) 13. Digital Up and Down Conversion 14. Error Correction Coding 15. Analog and TDMA Wireless Communications 16. CDMA Wireless Communications 17. OFDMA Wireless Communications 18. Radar Basics 19. Pulse Doppler Radar 20. FMCW Radar Signal Processing 21. Space-Time Adaptive Processing Radar (STAP) 22. Synthetic Array Radar (SAR) 23. Field Orientated Motor Control 24. Introduction to Video Processing 25. Introduction to Video Compression 26. Introduction to Machine Learning 27. Implementation using Digital Signal Processors 28. Implementation using FPGAs

Appendix A - Q Format Shift with Fractional Multiplication Appendix B - Evaluation of FIR Design Error Minimization Appendix C - Laplace transform Appendix D - Z transform Appendix E - Binary Field Arithmetic

Michael Parker is responsible for Intel's FPGA division digital signal processing (DSP) product planning. This includes Variable Precision FPGA silicon architecture for DSP applications, DSP tool development, floating point tools, IP and video IP. He joined Altera (now Intel) in January 2007, and has over 20 years of previous DSP engineering design experience with companies such as Alvarion, Soma Networks, Avalcom, TCSI, Stanford Telecom and several startup companies. He holds an MSEE from Santa Clara University, and BSEE from Rensselaer Polytechnic Institute.