Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems

Strategic Design and Optimization of Vedic Low Pass Filter for ECG Signals.- Computing Transient Response of Drain Current for High Electron Mobility Transistor in Presence of Hot Electrons.- An Approach for Alert Correlation using Arc Sight SIEM and Open Source NIDS.- High Impedance Fault Detection  in Microgrids Using Cross-alienation Coefficient.- Robust Image Hashing Using Chromatic Channel.- A Single Element Dual Feed MIMO Cylindrical Dielectric Resonator Antenna with High Isolation for 5.6GHz WLAN Application.- AlexNet-CNN based feature extraction and classification of multiclass ASL hand gestures.- Image Compression Based On DCT And Adaptive Grid Scanning.- Low Power Bandgap Reference Using Chopper Amplifier.- Analytical Investigation of Transconductance and Differential Conductance of Ultrathin ID-DG MOSFET with Gradual Channel Approximation.- FPGA Implementation of Optimized High Throughput  Radix-8based FFT Architecture.- Transportation Network Analysis using FuzzyLogic Through GIS Techniques: A Study of Central Kolkata.- Integration of IoT Based PLC for Smart Relaying of a PV-fed Induction Motor Driven Conveyor Belt.- Stacking Based Ensemble Learning for Improved Software Defect Prediction.- Design and Implementation of Single Stage Resonant Inverter for Electronic Ballast.

Dr. V. Nath was born in Gorakhpur (U.P.) India in 1976. He received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India, in 1998 and 2001. He received PGDCN (GM) from MMMUT Gorakhpur in 1999 and Ph.D. degree in VLSI Design & Technology from Dr. RML Avadh University Ayodhya in association with CEERI, Pilani, in 2008. From 2000 to 2001, he was Project Trainee in IC Design Group, CEERI, Pilani. Presently, he is Associate Professor in the Department of ECE, BIT Mesra Ranchi (JH) India, and joined this institute in 2006. His research interests include micro & nano-electronics, analog & digital VLSI design, ASICs, embedded systems designs, Internet of things & machine learning. He has to his credit around 195 publications in reputed Scopus & SCI journals and conferences, and 3 scholars were awarded Ph.D. degree under his supervision. He has successfully completed two R&D projects funded by DST New Delhi with DRDL Hyderabad and MHRD New Delhi, and the third project is in ongoing stage funded by RESPOND SAC ISRO Ahmedabad. He has received 100 crore projects as Co-PI in NM-ICPS (TIH) in BIT Mesra (Spokes) for development of e-farming platform for enhancement of production marketing and income of Indian farmers in August 2020. He is the editor of Nanoelectronics, Circuits & Communication Systems, Proceeding of NCCS-2015, NCCS-2017, NCCS-2018, & NCCS-2019 published in 2017, 2018, 2019 and 2020 & the editor of Microelectronics, Computing & Communication Systems, Proceeding of MCCS-2015, MCCS-2017, MCCS-2018 & MCCS-2019 published in 2017, 2018, 2019 & 2020 in Scopus book series: LNEE, Springer. He is a member of several professional societies and academic bodies including IETE, ISTE, ISVE and IEEE.
Prof. J.K. Mandal received his M.Sc. in Physics from Jadavpur University in 1986 and M.Tech. in Computer Science from the University of Calcutta and was awarded a Ph.D. in Computer