Routing Congestion in VLSI Circuits
Estimation and Optimization
(Sprache: Englisch)
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.
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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.
Klappentext zu „Routing Congestion in VLSI Circuits “
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
This book provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are equipped with the knowledge to prudently choose an approach that is appropriate to their design goals.
This work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step.
The subjects covered in this book include: a motivation that explains why the problem is important and how it will trend, definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
This work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step.
The subjects covered in this book include: a motivation that explains why the problem is important and how it will trend, definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Inhaltsverzeichnis zu „Routing Congestion in VLSI Circuits “
- Origins of Congestion.- Definitions/Descriptions of the Congestion Problem.
- Metrics for Congestion, and Relationship to Rent's Parameters.
- Impact of Congestion on Design Convergence and Yield.
- Impact of Congestion-Oblivious Upstream Optimization on Congestion.
- Impact of Scaling on Congestion.
- II: Estimation of Congestion.
- Post-Placement Metrics:Probabilistic Methods vs. Various Flavors of Fast Global Rouing; Distributed Metrics Based on Subject Graph Placement.
- Pre-Layout Structural Metrics.
- III: Optimization of Congestion.
- Congestion Relief and Routability Enhancement During Routing:Global Router Tricks, Pin Placement Perturbation, Layer Assignment, Interaction With Power Grid, Congestion Aware Buffering.
- Optimizing Congestion During Placement: Cell Bloating, Congestion Driven Cell Moves During Legalization, White Space Management, "Crowdedness" Balanced Min-Cut Partitioning.
- Congestion Metric-Driven Logic Synthesis: Applying Block-Level Routability/Interconnection Complexity Prediction Metrics During Logic Synthesis.
- Impact of Architectural Choices: Interconnection Complexity of Multi-Core Designs, Loosely Coupled GALS Systems, Systolic/SIMD DSP Processors; Interconnection Complexity of Layout Fabrics Such as Structured Asics.
Bibliographische Angaben
- Autoren: Prashant Saxena , Rupesh S. Shelar , Sachin Sapatnekar
- 2007, 250 Seiten, mit Abbildungen, Maße: 16,5 x 24,2 cm, Gebunden, Englisch
- Verlag: Springer
- ISBN-10: 0387300376
- ISBN-13: 9780387300375
Sprache:
Englisch
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